In recent, with the explosive growth of the market for mobile electronic devices using batteries, demands for digital circuits requiring less power consumption are increasing.
Power consumption of a digital circuit can be reduced by lowering its supply voltage. Upon usage, lowering the supply voltage to a level less than or near the threshold voltage of the semiconductor can minimize the power consumption of the circuit.
However, there is a problem in a sub/near-threshold operation that the performance of the circuit varies substantially compared to that in a super-threshold operation due to process variations, voltage fluctuations, and temperature variations. The variation of the circuit performance results in issues in determining the circuit's clock signal frequency.
The maximum speed of a digital circuit is determined by the critical path delay which is the longest delay of combinational circuits of the circuit. The period of the applied clock signal should be always longer than the critical path delay, or the circuit may malfunction. As a result, it will degrade the yield of the designed chip.
The simplest way to prevent the malfunctioning of the circuit is to stretch the period of the clock sufficiently. The cycle of the clock has to be set to the longest delay, i.e., critical path delay, considering the worst case variation.
However, such an approach greatly increases energy consumption. Since the period of the clock is set to the worst case, most circuits are usually in the idle state after finishing necessary operations, because the circuits are still left with as much time as the difference between the period of the clock and the actual critical path delay.
Even during that remaining time, a certain amount of current is still leaking. Due to the energy consumed by the active leakage current, the goal to design a low power circuit is not sufficiently satisfied. Since the circuit does not operate as fast as the potential speed of the circuit, time and other resources are wasted.
As described above, the problems of the malfunctioning of the circuit or the waste of energy become more serious as the supply voltage becomes lower due to temperature variation, variation of a supply voltage, and so on. Accordingly, there is a demand for a circuit and a method for generating an adaptive clock, which is capable of minimizing the time during which a circuit is in the idle state, by optimally adjusting a cycle of the clock depending on operation circumstances, so as to reduce energy consumption while not incurring malfunction.
With respect to a delay circuit for increasing a cycle of a clock, Korean Patent No. 10-0514414 describes a delay synchronized loop (DDL) circuit.
Korean Patent No. 10-0945793 also describes a delay synchronized loop (DDL) circuit.
An objective of the present disclosure is to provide an adaptive clock generating apparatus and a method thereof, which dynamically set the period of a clock along with changes in critical path delay of a synchronous circuit, so as to minimize energy consumption while preventing a clock synchronization error of a circuit.